In most computer or data processing systems, the main active memory, or random access memory (RAM), is a dynamic random access memory (DRAM). The structure of a DRAM is generally composed of a number of memory cells organized into a plurality of banks. Each bank corresponds to an array of the memory cells with each cell being respectively associated with a unique memory address. In particular, memory addresses within a bank are each designated by a row address and a column address, wherein each row address is defined as a memory page. Each page of memory, therefore, contains several memory locations corresponding to the different column designations within the page.
When performing a series of access requests, if a currently requested page is found in a same bank currently having another page open, such condition is known as a “page conflict,” whereupon the previously opened page must first be closed, or “precharged.” After precharging, the requested page may then be opened, or “activated,” and then the read or write operation is performed. A “page miss” occurs if the currently requested page is found in a bank which has no page open, thus requiring an activation procedure to be performed. A “page hit” is said to occur when a current memory access request is for a page which is already open from a previous memory access request.
Due to the extra processing which must be performed for page conflict and page miss memory accesses relative to page hit requests, the time needed to perform the former two processes is significantly greater than for the latter. In early stages of microprocessor technology development, requests to access a DRAM memory page, for both read and write operations, were received and fulfilled on a first in, first out basis. Such processing tends to be very inefficient, resulting in a large number of page misses and conflicts, and thus requiring an extensive dedication of processor and/or memory controller resources to precharging and activating memory pages.
More recently, more advanced processing methods have been developed in which memory access is based on priority. The priority of the access request may be based on various factors such as the type of device sending the request, the type of access requested, the memory address desired to be accessed by the request, etc. The problem with providing memory access strictly on priority, however, is that low priority requests may be denied access for unacceptably long periods of time.
Moreover, as each new generation of computers evolves, memory clock speeds, are increased significantly. As the speed of a memory's clock increases, the potential occurrences of and the time penalty for page miss memory operations, bank busy conflicts, and other conflicts also become increasingly significant. In particular, the data bus used to transfer information to and from each accessed memory location is idle during precharging, activating, waiting for bank availability, etc.
A solution is therefore needed to mitigate the drawbacks discussed above. In particular, memory processing efficiency would be greatly improved if the order of a sequence of received memory access requests could be rearranged to avoid or reduce conflicts. By avoiding or reducing conflicts, the memory data bus is more efficiently utilized in that idle time in the memory data bus is reduced or eliminated, which thereby effectively increases the memory bandwidth of the memory system and enables more memory access transactions to occur in a shorter amount of time than previously possible.